Bipolar junction transistors (BJTs) and varactors, have played an increasingly significant role in the semiconductor industry. The improvement of bipolar circuit performance, especially the operation speed, is an essential requirement for improving network communication systems and wireless systems. BJTs with silicon-germanium bases provide the desired device performance in such systems. For example, SiGe-based heterojunction bipolar transistors (HBTs) have recently achieved a current cut-off frequency (ft) of about 350 GHz.
As current density increases in the bipolar circuits, heat dissipation and parasitic resistance of the bipolar devices begin to impose more significant limitations on the device performance. High junction temperature and collector resistance degrade ft, and the maximum oscillation frequency (fmax) is in turn limited by ft as well as by the effective resistance-capacitance (RC) time constant.
Conventionally, the collector of the BJT or the n-type cathode of the varactor is contacted by a buried semiconductor layer (also referred to as sub-collector in a bipolar junction transistor) that is located in the semiconductor substrate underneath the collector of the BJT or the cathode of the varactor. Such a buried semiconductor layer extends laterally to a reach-through contact, which then extends vertically to a front surface of the semiconductor substrate and forms electrical connection with a metal contact that is located over the front surface of the substrate and is laterally offset from the collector of the BJT or the cathode of the varactor.
FIG. 1 shows a conventional heterojunction bipolar transistor (HBT), which comprises a collector 15, an intrinsic base 20, an extrinsic base 25, and an emitter 35 that is isolated from the extrinsic base by dielectric 30. Metal via contact 50 and electrode 55, which are located over a front surface of the semiconductor wafer 1 and are laterally aligned with the extrinsic base 25, directly form an electrical connection with the extrinsic base 25 of the HBT. Similarly, metal via contact 40 and electrode 60, which are located over a front surface of the semiconductor wafer 1 and are laterally aligned with the emitter 35, directly form an electrical connection with the emitter 35 of the HBT.
However, metal via contact 45 and electrode 65, which are located over a front surface of the semiconductor wafer 1, are laterally offset from the collector 15, and electrical connection therefore cannot be directly formed between the collector 15, the metal via contact 45 and the electrode 65.
In contrast, the collector 15 is first contacted by a buried semiconductor (or sub-collector) layer 18 located in the semiconductor wafer 1, which in turn contacts a reach-through implant region 43 that is isolated from the collector 15 by one or more shallow trench isolation regions 10 in the semiconductor wafer 1. The buried semiconductor layer 18 provides a horizontal conductive path from beneath the active region of the HBT to the reach-through implant region 43, while the reach-through implant region 43 provides a vertical conductive path from the buried semiconductor layer 18 to the metal via contact 45 as well as the electrode 65 on the front surface of the semiconductor wafer 1. Deep trench isolation 5 and shallow trench isolation 10 are also formed in the semiconductor wafer 1 to isolate the HBT transistor from adjacent devices. Specifically, the reach-through implant region 43 is defined by the surrounding shallow trench isolation 10.
Typically, the buried semiconductor layer 18 is first formed in the semiconductor substrate 1 by high-dose ion implantation followed by high temperature annealing and epitaxial deposition of a semiconductor device layer (not shown) thereon. Deep trench isolation regions 5 and shallow trench isolation regions 10 are then formed. Specifically, the deep trench isolation regions 5 extend through the semiconductor device layer (not shown) and the buried semiconductor layer 18 into the substrate 1, and the shallow trench isolation regions 10 extend only through the semiconductor device layer (not shown) and stop at the buried semiconductor layer 18. The shallow trench isolation regions 10 function to pattern the semiconductor device layer (not shown) and thereby define a device or collector region 15 and a reach-through contact region 43 therein. The reach-through contact region 43 is adjacent to, but is at the same time isolated from, the device or collector region 15 by one or more shallow trench isolation regions 10. Subsequently, dopant implantation and annealing are carried out in the reach-through contact region 43 to form a reach-through contact. The active components of the bipolar device are then formed over the device or collector region of the semiconductor device layer (not shown), followed by deposition of an interlevel dielectric (ILD) layer (not shown) over the entire structure and formation of metal via contacts 40, 45, and 50 through the ILD layer (not shown) to the front surface of the substrate 1 to provide electrical connections to various active components of the bipolar device, such as the collector 15, the base 25, and the emitter 35 of the HBT as shown in FIG. 1 or the cathode and anode of a varactor (not shown).
The high current density typically used in modern semiconductor circuitry generates substantial junction heat, which can only be dissipated into the bulk semiconductor substrate through the buried semiconductor layer. Since semiconductor materials are not ideal heat conductors, un-dissipated junction heat in turn causes significant increase in the junction temperature.
Further, the parasitic resistance of a bipolar device is composed of three major components: (1) the resistance of a vertical conductive path from the collector-base junction of a BJT (or the cathode-anode junction of a varactor) to the buried semiconductor layer, (2) the resistance of a horizontal conductive path along the buried semiconductor layer, and (3) the resistance of another vertical path from the buried semiconductor layer through the reach-through implant region to the metal contact located on the front surface of the substrate. Because semiconductor materials, which form the above-mentioned conductive paths in the conventional bipolar device, have relatively high resistance, the overall parasitic resistance in the conventional bipolar device is significant, which imposes limitation on the maximum oscillation frequency (fmax) of the bipolar device as the cut-off frequency (ft) of the device increases.
There is therefore a need to improve heat dissipation and reduce parasitic resistance in bipolar devices for enhancing the radio-frequency (RF) performance of such bipolar devices.